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integrated silicon solution, inc. www.issi.com 1 rev. a 12/19/07 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. is42s32800 features concurrent auto precharge ? clock rate:166/143 mhz ? fully synchronous operation ? internal pipelined architecture ? four internal banks (2m x 32bit x 4bank) ? programmable mode ? cas# latency: 2 or 3 burst length:1,2,4,8,or full page burst type: interleaved or linear burst burst-read-single-write burst stop function ? individual byte controlled by dqm0-3 ? auto refresh and self refresh ? 4096 refresh cycles/64ms (15.6s/row) ? single +3.3v 0.3v power supply ? interface:lvttl ? package: ? 86 pin tsop-2,0.50mm pin pitch 8x13mm, 90 ball bga, ball pitch 0.8mm pb-free package is available ? power down and deep power down mode ? partial array self refresh ? temperature compensated self refresh ? output driver strength selection ? please contact product manager for mobile function ? detail description the issi is42s32800 is a high-speed cmos con- fgured as a quad 2m x 32 dram with asynchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 2m x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits. read and write accesses start at a selected locations in a programmed sequence. accesses begin with the registration of a bankactive command which is then followed by a read or write command. the issi is42s32800 provides for programmable read or write burst lengths of 1,2,4,8,or full page, with a burst termination operation. an auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applica- tions requiring high memory bandwidth. 2m words x 32 bits x 4 banks (256-mbit) synchronous dram p january 2008
2 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 functional block diagram column count er address buffer a0 a9 bs0 bs1 dqm0~3 clock buffer command decoder sense ampl ifier row dec oder sense ampl ifier column decoder row decoder clk cke cs# ras# cas# we# dq0 dq3 1 sense ampl ifier col u m n de c o der row decoder sense amplifier column decoder row decoder 4096 x 512 x 32 cell arra y (bank #2) dq buffer a 10/ap refresh counter mode register control signal genera t or column decoder 4096 x 512 x 32 cell arra y (bank #0) 4096 x 512 x 32 cell arra y (bank #1) 4096 x 512 x 32 cell arra y (bank #3) a1 1
integrated silicon solution, inc. www.issi.com 3 rev. a 12/19/07 is42s32800 pin descriptions table 1.pin details of i s 42s32800 symbol type description clk input clock: clk is driven by the system clock.all sdram input signals are sampled on the positive edge of clk.clk also increments the internal burst counter and controls the output registers. c k e input clock enable: cke activates(high)and deactivates(low)the clk signal.if cke goes low syn- chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low.when all banks are in the idle state,deactivating the clock controls the entry to the power down and self refresh modes.cke is synchronous except after the device enters power down and self refresh modes,where cke becomes asynchronous until exiting the same mode. the input buffers,including clk,are disabled during power down and self refresh modes,providing low standby power. bs0,bs1 input bank select: bs0 and bs1 defines to which bank the bankactivate,read,write,or bankprecharge command is being applied. a0-a11 input address inputs: a0-a11 are sampled during the bankactivate command (row address a0-a11)and read/write command (column address a0-a 8 with a10 defining auto precharge) to select one location in the respective bank.during a precharge command,a10 is sampled to determine if all banks are to be precharged (a10 =high). the address inputs also provide the op-code during a mode register set . c s # input chip select: cs#enables (sampled low)and disables (sampled high)the command decoder.all commands are masked when cs#is sampled high.cs#provides for external bank selection on systems with multiple banks.it is considered part of the command code. ras# input row address strobe: the ras#signal defines the operation commands in conjunction with the cas#and we#signals and is latched at the positive edges of clk.when ras# and cs#are as- serted ?low?and cas#is asserted ?high,?either the bankactivate command or the precharge command is selected by the we#signal.when the we#is asserted ?high,?the bankactivate com- mand is selected and the bank designated by bs is turned on to the active state.when the we#is asserted ?low,?the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. cas# input column address strobe: the cas#signal defines the operation commands in conjunction with the ras#and we#signals and is latched at the positive edges of clk. when ras#is held ?high?and cs#is asserted ?low,?the column access is started by asserting cas#?low.?then,the read or write command is selected by asserting we# ?low?or ?high.? w e # input write enable: the we#signal defines the operation commands in conjunction with the ras#and cas#signals and is latched at the positive edges of clk.the we#input is used to select the bankactivate or precharge command and read or write command. dqm0-3 input data input/output mask: dqm0-dqm3 are byte specific,nonpersistent i/o buffer controls. the i/o buffers are placed in a high-z state when dqm is sampled high.input data is masked when dqm is sampled high during a write cycle.output data is masked (two-clock latency)when dqm is sampled high during a read cycle.dqm3 masks dq31-dq24,dqm2 masks dq23-dq16,dqm1 masks dq15-dq8,and dqm0 masks dq7-dq0. dq0-31 input/output data i/o: the dq0-31 input and output data are synchronized with the positive edges of clk.the i/os are byte-maskable during reads and writes.
4 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 pin configurations 86 pin tsop - type ii for x32 pin descriptions a0-a11 row address input a0-a8 column address input ba0, ba1 bank select address dq0 to dq31 data i/o c l k system clock input c k e clock enable cs chip select ras row address strobe command cas column address strobe command v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v dd dqm0 we cas ras cs a11 ba0 ba1 a10 a0 a1 a2 dqm2 v dd nc dq16 v ss q dq17 dq18 v dd q dq19 dq20 v ss q dq21 dq22 v dd q dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v dd q dq30 dq29 v ss q dq28 dq27 v dd q dq26 dq25 v ss q dq24 v ss we write enable dqm0-dqm3 x32 input/output mask v dd power v s s ground v ddq power supply for i/o pin vss q ground for i/o pin n c no connection
integrated silicon solution, inc. www.issi.com 5 rev. a 12/19/07 is42s32800 pin configuration package code: b 90 ball fbga (top view) (8.00 mm x 13.00 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r dq26 dq28 v ssq v ssq vddq vs s a4 a7 clk dqm1 vddq v ssq v ssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 vddq dq15 vs s v ssq dq25 dq30 nc a3 a6 nc a9 nc vs s dq9 dq14 v ssq vs s vdd vddq dq22 dq17 nc a2 a10 nc ba0 cas vdd dq6 dq1 vddq vdd dq23 v ssq dq20 dq18 dq16 dqm2 a0 ba1 cs we dq7 dq5 dq3 v ssq dq0 dq21 dq19 vddq vddq v ssq vdd a1 a11 ras dqm0 v ssq vddq vddq dq4 dq2 pin descriptions a0-a11 row address input a0-a8 column address input ba0, ba1 bank select address dq0 to dq31 data i/o c l k system clock input c k e clock enable cs chip select ras row address strobe command cas column address strobe command we write enable dqm0-dqm3 x32 input/output mask v dd power v s s ground v ddq power supply for i/o pin vss q ground for i/o pin n c no connection
6 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 2 shows the truth table for the operation commands. t a ble 2.t ruth t a ble (note (1),(2)) note: 1 . v =valid,x =don ?t care,l =logic low,h =logic high 2 . cken signal is input level when commands are provided. cken-1 signal is input level one clock cycle before the commands are provided. 3 . these are states of bank designated by bs signal. 4. device state is 1,2,4,8,and full page burst operation. 5 . power down mode can not enter in the burst operation. when this command is asserted in the burst cycle,device state is clock suspend mode. 6 . dqm0-3 command state cken-1 c k e d q m (6) bs0,1 a10 a11,a9-0 cs# ras# cas# w e # bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) hx x v l l h l l write and auto precharge active (3) hx x v h l h l l read active (3) hx x v l l h l h read and autoprecharge active (3) hx x v h l h l h mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) hx x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x x x x x power down mode entry any (5) hl x x x x h x x x lh h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x column address (a0 ~a 8 ) column address (a0 ~a 8 )
integrated silicon solution, inc. www.issi.com 7 rev. a 12/19/07 is42s32800 commands 1 bankactivate (ras#=?l?,cas#=?h?,we#=?h?,bs =bank,a0-a11 =row address) the bankactivate command activates the idle bank designated by the bs0,1 (bank select) signal.by latching the row address on a0 to a11 at the time of this command,the selected row access is initiated.the read or write operation in the same bank can occur after a time delay of t r c d(min.)from the time of bank activation.a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure).the minimum time interval between successive bankactivate commands to the same bank is defined by trc(min.).the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back activation of the four banks. trr d(min.)specifies the minimum time required between activating different banks. after this command is used,the write command and the block write command perform the no mask write operation. clk address t0 t1 t2 t3 tn+3 tn+4 tn+5 tn+6 .. .. .. .. .. .. .. command . . .. .. .. .. .. .. .. .. .. .. .. .. .. nop nop nop nop ras# - cas# delay ( t rcd ) ras#- ras# delay time ( t rrd ) ras# cycle time ( t rc ) bank a row addr . bank a col addr . bank b row addr . bank a row addr . bank a activate r/w a with autoprecharge bank b activate bank a activate auto precharge begin :"h" or "l" bank 2 bankprecharge command (ras#=?l?,cas#=?h?,we#=?l?,bs =bank,a10 =?l?) the bankprecharge command precharges the bank disignated by bs0,1 signal.the precharged bank is switched from the active state to the idle state.this command can be asserted anytime after tras(min.)is satisfied from the bankactivate command in the desired bank.the maximum time any bank can be active is specified by tras(max.).therefore,the precharge function must be performed in any active bank within tras(max.).at the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
8 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 3 prechargeall command (ras#=?l?,cas#=?h?,we#=?l?,bs =don t care,a10 =?h?) the precharge all command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras#=?h?,cas#=?l?,we#=?h?,bs =bank,a10 =?l?,a0-a 8 =column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank.the bank must be active for at least trcd(min.) before the read command is issued.during read bursts, the valid data-out element from the starting column address will be available following the cas# latency after the issue of the read command.each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure).the dqs go into high-impedance at the end of the burst unless other command is initiated. the burst length,burst sequence,and cas# latency are determined by the mode register which is already programmed.a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
integrated silicon solution, inc. www.issi.com 9 rev. a 12/19/07 is42s32800 t0 t2 t1 t3 t4 t5 t6 t7 t8 read a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 clk command cas# latency=2 t ck2 , dq s cas# latency=3 t ck3 , dq s read a read b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 3 2 dout b clk command cas# latency=2 t ck2 , dq s cas# latency=3 t ck3 , dq s t0 t2 t1 t3 t4 t5 t6 t7 t8 burst read operation(burst length =4,cas#latency =2,3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i.e.dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length.it may be interrupted by a bankprecharge/prechargeall command to the same bank too.the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). read interrupted by a read (burst length =4,cas#latency =2,3) the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command.the dqms must be asserted (high)at least two clocks prior to the write command to suppress data-out on the dq pins.to guarantee the dq pins against i/o contention,a single cycle with high-impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures).if the data output of the burst read occurs at the second clock of the burst write,the dqms must be asserted (high)at least one clock prior to the write command to avoid internal bus contention.
10 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 read a nop nop nop nop write b nop nop dqm command dq? s nop dout a dinb 2 dinb 1 dinb 0 must be hi-z before the w rite com mand : "h" or "l" clk t0 t2 t1 t3 t4 t5 t6 t7 t8 clk dqm command nop nop nop nop nop banka activ a t e din a 0 din a 1 din a 2 din a 3 1 clk interval cas# latency=2 read a writea : "h" or "l" nop t0 t2 t1 t3 t4 t5 t6 t7 t8 tck2, dqs clk dqm command nop rea d a nop nop nop nop din b 0 din b 1 din b 2 din b 3 cas# latency=2 nop nop : "h" or "l" t ck2 , dq? s t0 t2 t1 t3 t4 t5 t6 t7 t8 writeb tck2, dqs read to write interval (burst length = 4,cas#latency =3) read to write interval (burst length = 4,cas#latency =2) read to write interval (burst length = 4,cas#latency =2) a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank.the following figure shows the optimum time that bankprecharge/prechargeall command is issued in different cas#latency.
integrated silicon solution, inc. www.issi.com 11 rev. a 12/19/07 is42s32800 read to precharge (cas#latency =2,3) 5 write command (ras#=?h?,cas#=?l?,we#=?l?,bs =bank,a10 =?l?,a0-a 8 =column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.the bank must be active for at least trcd(min.)before the write command is issued.during write bursts, the first valid data-in element will be registered coincident with the write command.subsequent data elements will be registered on each successive positive clock edge (refer to the following figure).the dqs remain with high- impedance at the end of the burst unless another command is initiated.the burst length and burst sequence are determined by the mode register,which is already programmed.a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command read a nop nop nop nop activate nop no p precharge dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address t rp bank, col a ba nk(s ) cas# latency=2 t ck2 , dq s cas# latency=3 t ck3 , dq s t0 t2 t1 t3 t4 t5 t6 t7 t8 bank, row clk command din a 3 no p writea i nop no p no p no p no p nop nop din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don?t care t0 t2 t1 t3 t4 t5 t6 t7 t8 burst write operation (burst length =4,cas#latency =2,3) a write burst without the autoprecharge function may be interrupted by a subsequent write, bankprecharge/ prechargeall,or read command before the end of the burst length.an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure).
12 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 clk command din b 2 nop writea writeb nop nop nop nop nop nop din a 0 din b 0 din b 1 dq? s din b 3 1 clk interval t0 t2 t1 t3 t4 t5 t6 t7 t8 clk command t 0t 1 t 2t 3 t 4t 5 t 6t 7 t 8 nop writea nop nop nop nop nop read b nop din a 0 don?t care dout b 2 dout b 0 dout b 1 dout b 3 din a 0 don?t care don?t care dout b 2 dout b 0 dout b 1 dout b 3 di n input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. input data for the write is masked. cas# latency=2 t ck2 , dq? s cas# latency=3 t ck3 , dq? s clk write command bank (s) row nop nop precharge n o p n o p activate bank col n din nn + 1 dqm address dq t wr t rp : dont care t0 t2 t1 t3 t4 t5 t6 write interrupted by a write (burst length =4,cas#latency =2,3) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.in order to avoid data contention,input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure).once the read command is registered,the data inputs will be ignored and writes will not be executed. write interrupted by a read (burst length =4,cas#latency =2,3) the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals t w r/ tck rounded up to the next whole number.in addition,the dqm signals must be used to mask input data,starting with the clock edge following the last data-in element and ending with the clock edge on which the bankprecharge/ prechargeall command is entered (refer to the following figure). note: the dqms can remain low in this example if the length of the write burst is 1 or 2. write to precharge
integrated silicon solution, inc. www.issi.com 13 rev. a 12/19/07 is42s32800 don t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop note: dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) 6 concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. icsi sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is regis-tered. read with auto precharge interrupted by a read interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. read with auto precharge interrupted by a write clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm note: 1. dqm is high at t2 to prevent d out -a+1 from contending with d in -d at t4. bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care
14 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 write with auto precharge interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out ap- pearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. write with auto precharge interrupted by a read interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m. write with auto precharge interrupted by a write d in a d in d + 2 d in d + 3 don?t care t2 t1 t4 t3 t6 t5 t0 command t7 bank n nop d in d + 1 write - ap bank n nop nop nop note: 1. dqm is low. bank n , col a bank m , col d write - ap bank m nop d in a + 1 d in a + 2 d in d page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m bank m address internal states t page active write with burst of 4 interrupt burst, write-back precharge t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop note: 1. dqm is low. bank n , col a bank m , col d read - ap bank m nop nop page active read with burst of 4 internal states t page active write with burst of 4 interrupt burst, write-back precharge wr - bank n rp - bank n t t rp - bank m t7 bank n bank m address clk dq d in a d in a + 1 d out d d out d + 1 cas latency = 3 (bank m ) don?t care
integrated silicon solution, inc. www.issi.com 15 rev. a 12/19/07 is42s32800 7 mode register set command (ras#=?l?,cas#=?l?,we#=?l?,bs0,1 and a11-a0 =register data) the mode register stores the data for controlling the various operating modes of sdram.the mode register set command programs the values of cas#latency,addressing mode and burst length in the mode register to make sdram useful for a variety of different applications.the default values of the mode register after power-up are undefined;therefore this command must be issued at the power-up sequence.the state of pins bs0,1 and a11~a0 in the same cycle is the data written to the mode register.one clock cycle is required to complete the write in the mode register (refer to the following figure).the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.
16 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 mode register set cycle the mode register is divided into various fields depending on functionality. *note:rfu (reserved for future use)should stay 0 during mrs cycle. ?d ?d ?d ?d ?d b u rs t le ng t h f i e l d ( a 2 ~ a 0 ) t h i s f i el d spec ifie s the d a ta le ng th o f c o lu mn acces s us ing t he a 2 ~a0 p i ns and s e le c t s the bu rst l eng th t o be 2 , 4,8,or full p a g e. ras# clk cke cs# cas# we# addr. dqm dq t ck2 clock min. address key t rp hi-z precharge all mode register set command any command t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 t10 a 2 a 1 a0 burst length 0 001 0 012 0 104 0 118 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page address bs0,1 a11/a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu* wbl test mode cas latency b t burst length
integrated silicon solution, inc. www.issi.com 17 rev. a 12/19/07 is42s32800 data n 0 1234 567 - 2 5 5 2 5 6 2 5 7 - column address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n +255 n n +1 - 2 words: burst length 4 words: 8 words: full page: column address is repeated until terminated. data n column address burst lengt h data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0# 4 words data 2 a7 a6 a5 a4 a3 a2 a1# a0 data 3 a7 a6 a5 a4 a3 a2 a1# a0# 8 words data 4 a7 a6 a5 a4 a3 a2# a1 a0 data 5 a7 a6 a5 a4 a3 a2# a1 a0# data 6 a7 a6 a5 a4 a3 a2# a1# a0 data 7 a7 a6 a5 a4 a3 a2# a1# a0# ? burst type field (a3) the burst type can be one of two modes,interleave mode or sequential mode. ?addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device.the internal column address is varied by the burst length as shown in the following table.when the value of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective. ? addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. ? cas#latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data.the minimum whole value of cas#latency depends on the frequency of clk.the minimum whole value satisfying the following formula must be programmed into this field. t cac (min)<=cas#latency x t ck a 6 a 5 a 4 cas#latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved a 3 burst type 0 sequential 1 interleave
18 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to ?00?in normal operation. ? write burst length (a9) this bit is used to select the burst write length. 8 no-operation command (ras#=?h?,cas#=?h?,we#=?h?) the no-operation command is used to perform a nop to the sdram which is selected (cs# is low).this prevents unwanted commands from being registered during idle or wait states. 9 burst stop command (ras#=?h?,cas#=?h?,we#=?l?) the burst stop command is used to terminate either fixed-length or full-page bursts.this command is only effective in a read/write burst without the auto precharge function.the terminated read burst ends after a delay equal to the cas#latency (refer to the following figure).the termination of a write burst is shown in the following figure. termination of a burst read operation (burst length > 4 ,cas#latency =2,3) termination of a burst write operation (burst length =x) cl k comman d t 0t 1 t 2t 3 t 4t 5 t 6t 7 t 8 rea d a nop nop nop nop nop nop nop c a s# l a t e n c y = 2 tck2,dq?s dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 c a s# l a t e n c y = 3 tck3,dq?s the burst ends after a delay equal to the cas# latency. burst stop cl k comman d t 0 t 1 t 2 t 3t 4 t 5t 6 t 7t 8 nop w r i t e a nop nop nop nop nop nop b u r s t sto p c a s# l a t e n c y=2 , 3 dq?s di n a 0 di n a 1 di n a 2 d o n?t c a r e input data for the write is masked. a 8 a 7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only a 9 write burst length 0 burst 1 single bit
integrated silicon solution, inc. www.issi.com 19 rev. a 12/19/07 is42s32800 1 0 device deselect command (cs#=?h?) the device deselect command disables the command decoder so that the ras#,cas#,we# and address inputs are ignored,regardless of whether the clk is enabled.this command is similar to the no operation command. 1 1 autorefresh command (ras#=?l?,cas#=?l?,we#=?h?,cke =?h?) the autorefresh command is used during normal operation of the sdram and is analogous to cas#-before- ras#(cbr)refresh in conventional drams.this command is non-persistent,so it must be issued each time a refresh is required.the addressing is generated by the internal refresh controller.this makes the address bits a ?don ?t care?during an autorefresh command.the internal refresh counter increments automatically on every auto refresh cycle to all of the rows.the refresh operation must be performed 4096 times within 64ms (32ms for industrial grade) . the time required to complete the auto refresh operation is specified by trc(min.).to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle).this command must be followed by nops until the auto refresh operation is completed.the precharge time requirement,trp(min),must be met before successive auto refresh operations are performed. 1 2 selfrefresh entry command (ras#=?l?,cas#=?l?,we#=?h?,cke =?l?) the selfrefresh is another refresh mode available in the sdram.it is the preferred refresh mode for data retention and low power operation.once the selfrefresh command is registered,all the inputs to the sdram become ?don ?t care?with the exception of cke,which must remain low.the refresh addressing and timing is internally generated to reduce power consumption.the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 1 3 selfrefresh exit command (cke =?h?,cs#=?h?or cke =?h?,ras#=?h?,cas#=?h?,we#=?h?) this command is used to exit from the selfrefresh mode.once this command is registered, nop or device deselect commands must be issued for trc(min.)because time is required for the completion of any bank currently being internally refreshed.if auto refresh cycles in bursts are performed during normal operation,a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 1 4 clock suspend mode entry /powerdown mode entry command (cke =?l?) when the sdram is operating the burst cycle,the internal clk is suspended(masked)from the subsequent cycle by issuing this command (asserting cke ?low?).the device operation is held intact while clk is suspended.on the other hand,when all banks are in the idle state,this command performs entry into the powerdown mode.all input and output buffers (except the cke buffer)are turned off in the powerdown mode.the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms)since the command does not perform any refresh operations. 1 5 clock suspend mode exit /powerdown mode exit command when the internal clk has been suspended,the operation of the internal clk is einitiated from the subsequent cycle by providing this command (asserting cke ?high?).when the device is in the powerdown mode,the device exits this mode and all disabled buffers are turned on to the active state.t pde (min.)is required when the device exits from the powerdown mode.any subsequent commands can be issued after one clock cycle from the end of this command. 1 6 data write /output enable,data mask /output disable command (dqm =?l?,?h?) during a write cycle,the dqm signal functions as a data mask and can control every word of the input data.during a read cycle,the dqm functions as the controller of output buffers.dqm is also used for device selection,byte selection and bus control in a memory system.
20 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 absolute maximum ratings (1) dc recommended operating conditions symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ddq supply voltage for dq 3.0 3.3 3.6 v v ih high level input voltage (all inputs) 2.0 ? v dd + 0.3 v v il low level input voltage (all inputs) - 0.3 ? +0.8 v notes: 1 . all voltages are referenced to v ss =0v 2. v ih (overshoot): v ih (max) = v dd + 2v (pulse width 3ns) 3. v il (undershoot): v il (min) = - 2v (pulse width 3ns) capacitance characteristics (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) symbol parameter min. max. unit c in input capacitance, address & control pin 2.5 3.8 pf c clk i nput capacitance, clk pin 2.5 3.5 pf c i / o data input/output capacitance 4.0 6.0 pf symbol parameters rating unit v dd supply voltage (with respect to v ss ) ?0.5 to +4.6 v v ddq supply voltage for output (with respect to v ssq ) ?0.5 to +4.6 v v i input voltage (with respect to v ss ) ?0.5 to v dd +0.5 v v o output voltage (with respect to v ssq ) ?1.0 to v ddq +0.5 v i o short circuit output current 50 m a p d power dissipation ( t a = 25 c) 1w t opt operating temperature com. 0 to +70 c ind. -40 to +85 t stg storage temperature ?65 to +150 c notes: 1 . exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to abso lute maximum rating conditions for extended periods may affect device reliability.
integrated silicon solution, inc. ? www .issi.com 21 re v . a 12/19/07 is42s32800 - 6/7 description/test condition symbol max. unit note operating current t rc t rc (min), outputs open, burst = 2 1 bank operation i cc1 135/125 3 precharge standby current in power down mode t ck = 15ns, cke v il (max) i cc2p 3 precharge standby current in power down mode t ck = , cke v il (max) i cc2ps 3 precharge standby current in non-power down mode t ck = 15ns, cs# v ih (min), cke v ih input signals are changed once during 30ns. i cc2n 30 3 precharge standby current in non-power down mode t ck = , clk v il (max), cke v ih i cc2ns 20 active standby current in power down mode ck e v il (max), t ck = 15ns i cc3p 4m a3 active standby current in power down mode cke& clk v il (max), t ck = i cc3ps 3 active standby current in non-power down mode cke v ih (min), cs# v ih (min), t ck = 15ns i cc3n 45 active standby current in non-power down mode cke v ih (min), clk v il (max), t ck = i cc3ns 30 operating current (burst mode) t ck =t ck (min), outputs open, full page i cc4 180/150 3, 4 refresh current t rc t rc (min) i cc5 300/270 3 self refresh current ck e 0.2v i cc6 1 3 parameter description min. max. unit note i il input leakage current (0v v in v dd , all other pins not under test = 0v ) - 10 +10 a i ol 2.4 v v oh lvttl output "h" level voltage ( i out = -2ma ) 3 3 v ol lvttl output "l" level voltage ( i out = 2ma ) 0.4 v output leakage current (0v v out v dd , dq disable ) - 10 + 10 a d.c. electrical characteristics (recommended operating conditions ) 8 8 8 8 active all banks
22 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 - 6/7 symbol a.c. parameter min. max. unit note t rc row cycle time (same bank) 60/70 9 t rrd row activate to row activate delay (dif ferent banks) 12/14 9 t rcd ras# to cas# delay (same bank) 1 8 /20 9 t rp precharge to refresh/row activate command (same bank) 1 8 /20 9 t ras row activate to precharge time (same bank) 42/45 120,000 9 t ck2 clock cycle tim e cl* = 2 7.5/10 t ck3 cl* = 3 6/7 ns access time from clk 9 t ac (positive edge) 5.5/5.5 t oh data output hold time 2/2 .5 9 t ch clock high time 2.5/2.5 10 t cl clock low time 2.5/2.5 10 t is data/address/control input set-up time 2.0 / 2.0 10 t ih data/address/control input hold time 1 10 t lz data output low impedance 1 9 t hz data output high impedance 5.4 8 t wr write recovery time 2 t ccd cas# to cas# delay time 1 clk t mrs mode register set cycle time 2 * cl is cas# latency . e ac electrical characteristics (recommended operating conditions) 5,6,7,8 note: 1 . stress greater than those listed under ?absolute maximum ratings?may cause permanent damage to the device. 2 . all voltages are referenced to vss. 3 . these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tck and trc. input signals are 2 cycles during tck. 4 . these parameters depend on the output loading.specified values are obtained with the output open. 5 . power-up sequence is described in note 11.
integrated silicon solution, inc. www.issi.com 23 rev. a 12/19/07 is42s32800 (n otes continued) 6. a.c. test conditions l vttl interf a c e reference level of output signals 1.4v /1.4v output load reference to the under output load input signal levels 2.4v /0.4v transition time (rise and fall)of input signals 1ns reference level of input signals 1.4v 1.4v 50 ? output 30pf z0= 50 ? l vttl a.c. t est load 7. transition times are measured between vih and vi l.transition(rise and fall)of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. if clock rising time is longer than 1 ns,(t r /2 -0.5)ns should be added to the parameter. 10. assumed input rise and fall time t t (t r &t f )=1 ns if t r or t f is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously)when all input signals are held ?nop?state and both cke =?h?and dqm =?h.?the clk signals must be started at the same time. 2) after power-up,a pause of 200 seconds minimum is required.then,it is recom mended that dqm is held ?high?(v dd levels)to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device.
24 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 t i ming w avef orms figure 1.ac parameters for write timing (burst length=4,cas#latency=2) -5 , , -7 , x x bs0,1 t ch t cl t ck2 t is t is t ih begin auto precharge bank a begin auto precharge bank b t is t ih t is rbx cax rbx cbx ra y ca y raz rby t rcd t dal t rc t is t ih t wr t rp t rrd ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 a y 0 a y 1 a y 2 a y 3 activate command bank a w rite with auto precharge command bank a activate command bank b w rite with auto precharge command bank b activate command bank a wr i t e co mmand bank a precharge command bank a activate command bank a activate command bank b clk cke cs# ras# cas# we# a ddr. dqm dq hi-z t0 t2 t1 t3 t4 t5 t6 t7 t9 t8 t12 t1 1 t10 t14 t13 t15 t16 t17 t18 t19 t21 t20 t22
integrated silicon solution, inc. www.issi.com 25 rev. a 12/19/07 is42s32800 figure 2.ac parameters for read timing (burst length=2,cas#latency=2) a10 a 0 -a9 dq t ch t cl t ck2 t is t is t ih b e gin a u t o prec h a rge bank b t ih t ih t is rax rax cax rbx rbx cbx ray ray t rrd t ras t rc t rcd t ac2 t lz t oh t hz ax0 ax1 bx0 bx1 t rp activate com m a n d bank a rea d com m a n d bank a activate c o mmand bank b r e ad with a u to precharge com m a n d bank b p r ech a rge com m a n d bank a activate com m a n d bank a hi - z t ac2 t hz t0 t2 t1 t3 t4 t5 t6 t7 t9 t8 t12 t11 t10 t13 bs0,1 clk cke cs# ras# cas# we# dqm
26 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 a10 a 0 -a9 dq m dq t ck2 rax rax cax t rp t rc ax0 ax1 ax2 ax3 pre c harge a l l c o m m and auto refresh com m a n d auto refresh c o mmand activate c o mmand bank a rea d c o mmand bank a t rc t0 t2 t1 t3 t4 t5 t6 t7 t9 t8 t12 t1 1 t10 t14 t13 t15 t16 t17 t18 t19 t21 t20 t22 bs0,1 clk cke cs# ras# cas# we# dq figure 3.auto refresh (cbr) (burst length=4,cas#latency=2)
integrated silicon solution, inc. www.issi.com 27 rev. a 12/19/07 is42s32800 figure 4.power on sequene and auto refresh (cbr) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq high level is required minimum of 2 refresh cycles are required t mrs t rp high level is necessary t rc address key inputs be stable for 200us precharge all banks must command 1st auto command refresh 2nd auto refresh command mode set command command register hi-z b s0, 1
28 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 5.self refresh entry &exit cycle note:to enter selfrefresh mode 1 . cs#,ras#&cas#with cke should be low at the same clock cycle. 2 . after 1 clock cycle,all the inputs including the system clock can be don ?t care except for cke. 3 . the device remains in selfrefresh mode as long as cke stays ?low?. once the device enters selfrefresh mode,minimum tras is required before exit from selfrefresh. to exit selfrefresh mode 1 . system clock restart and be stable before returning cke high. 2 . enable cke and cke should be set high for minimum time of tsrx . 3 . cs#starts from high. 4 . minimum trc is required after cke going high to complete selfrefresh exit. 5 . 2048 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst ref resh. clk cke cs# ras # c a s# b s 0,1 a 0 -a9 we# dqm dq * note 1 *note 2 t is *note 3 *note 4 t rc(min) *note 7 *note 5 *note 6 *note 8 *note 8 hi-z hi-z selfrefresh enter self r efresh e x i t auto refresh t srx t pde t0 t2 t1 t3 t4 t5 t6 t7 t9 t8 t12 t11 t10 t14 t13 t15 t16 t17 t18 t19
integrated silicon solution, inc. www.issi.com 29 rev. a 12/19/07 is42s32800 figure 6.2.clock suspension during burst read (using cke) (burst length=4,cas#latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t 2 1 t2 2 t ck2 rax rax cax hi-z ax0 ax1 ax2 ax3 activate c o mmand bank a rea d c o mmand bank a clock suspend 1 cycl e t hz clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq clock suspend 2 cycl e clock suspend 3 cycl e note: cke to clk disable/enable =1 clock
30 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 6.3.clock suspension during burst read (using cke) (burst length=4,cas#latency=3) note: cke to clk disable/enable =1 clock t 0 t 1 t 3t 4 t 5t 6 t 7t 8 t 9t 1 0 t 1 1 t 1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t 2 1 t2 2 t ck3 rax rax cax hi -z ax0 ax1 ax2 ax3 t hz t 2 clock suspend 1 cycl e clock suspend 2 cycl e clock suspend 3 cycl e activate c o mmand bank a rea d c o mmand bank a clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z
integrated silicon solution, inc. www.issi.com 31 rev. a 12/19/07 is42s32800 t 0 t 1 t 2t 3t 4 t 5t 6t 7t 8t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t2 2 t ck2 rax rax cax dax0 dax1 dax2 dax3 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a w rite c o mmand bank a clock suspend 1 cycl e clock suspend 2 cycl e clock suspend 3 cycl e figure 7.2.clock suspension during burst write (using cke) (burst length=4,cas#latency=2) note: cke to clk disable/enable =1 clock
32 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 7.3.clock suspension during burst write (using cke) (burst length=4,cas#latency=3) note: cke to clk disable/enable =1 clock t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t 2 1 t2 2 dax0 dax1 dax2 dax 3 t ck3 rax rax cax clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a clock suspend 1 cycl e clock suspend 2 cycl e clock suspend 3 cycl e wr i t e c o mmand bank a
integrated silicon solution, inc. www.issi.com 33 rev. a 12/19/07 is42s32800 t 0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 t is t pde rax rax cax t hz ax3 ax2 ax1 ax0 p o wer d o w n mode entry p o w e r d own m o d e entry mode exit clock mask start stand b y any valid active stand b y clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a rea d c o mmand bank a p o w e r d own mode exit p o w e r d own clock mask end pre c harge c o m m and bank a prec h a r g e c o mmand figure 8.power down mode and clock mask (burst lenght=4, cas#latency=2)
34 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 9.2.random column read (page within same bank) (burst length=4,cas#latency=2) t 0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 aw0 aw1 aw2 aw3 a x 0 a x 1 ay0 ay1 ay2 ay3 raw raw caw c a x cay caz az0 az1 az2 az3 activate raz raz clk cke cs# ras # cas # we# ba0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a rea d c o mmand bank a pre c harge com m a n d bank a rea d c o mmand bank a c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a
integrated silicon solution, inc. www.issi.com 35 rev. a 12/19/07 is42s32800 figure 9.3.random column read (page within same bank) (burst length=4,cas#latency=3) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 2 2 t ck3 aw0 aw1 aw2 aw3 a x 0 a x 1 ay0 ay1 ay2 ay3 raw raw caw cax cay caz raz raz az0 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a activate c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a pre c harge com m a n d bank a
36 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 10.2.random column write (page within same bank) (burst length=4,cas#latency=2) t 0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 dbw0 d b x 0 d b x 1 dby0 rbw cbw cbx cb y cb z rbz rb z rbw dbw1 dbw2 dbw3 dby1 dby2 dby3 dbz0 dbz1 dbz2 dbz3 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a wr i t e c o mmand bank b w rite c o mmand bank b wr i t e c o mmand bank b activate c o mmand bank a activate c o mmand bank b pre c harge com m a n d bank b
integrated silicon solution, inc. www.issi.com 37 rev. a 12/19/07 is42s32800 figure 10.3.random column write (page within same bank) (burst length=4,cas#latency=3) t 0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck3 dbw0 dbx0 dbx1 rbw cbw cbx cby cbz dbz0 rbz rbz rbw dbz1 dbz2 dbw1 dbw2 dbw3 dby0 dby1 dby2 dby3 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a wr i t e c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b activate c o mmand bank a activate c o mmand bank b pre c harge com m a n d bank b
38 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 11.3.random row read (interleaving banks) (burst length=8,cas#latency=3) t 0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck3 bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby cby hig h rax ax7 by0 ax2 ax3 ax4 ax5 ax6 cbx cax rax rby t rcd t ac3 t rp clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a rea d c o mmand bank a pre c harge c o m m and bank a activate com m a n d bank b activate c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b pre c harge c o m m and bank b
integrated silicon solution, inc. www.issi.com 39 rev. a 12/19/07 is42s32800 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck2 dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray cay rbx dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day3 day0 day1 day2 day4 t wr* t rp t wr* * t wr > t wr (min.) clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a w rite c o mmand bank a activate c o mmand bank a activate c o mmand bank a pre c harge c o m m and bank a w rite c o mmand bank b activate c o mmand bank b pre c harge c o m m and bank b hig h figure 12.2.random row write (interleaving banks) (burst length=8,cas#latency=2)
40 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 12.3.random row write (interleaving banks) (burst length=8,cas#latency=3) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck3 dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray cay rbx dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day3 day0 day1 day2 t wr* t rp t wr* * t wr > t wr (min.) clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite com m a n d bank a w rite c o mmand bank a activate c o mmand bank a activate c o mmand bank a pre c harge com m a n d bank a wr i t e c o mmand bank b activate c o mmand bank b pre c harge com m a n d bank b hig h
integrated silicon solution, inc. www.issi.com 41 rev. a 12/19/07 is42s32800 t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 ax0 ax1 ax2 ax3 d a y 0 day1 az3 day3 az0 az1 rax rax cax cay caz clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a activate c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a the write data is m a sked w i th a zero c l o c k laten c y t h e read data is m a sked with a two c l o c k laten c y figure 13.2.read and write cycle (burst length=4,cas#latency=2)
42 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 13.3.read and write cycle (burst length=4,cas#latency=3) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck3 ax0 ax1 ax2 ax3 d a y 0 day1 az3 day3 az0 az1 rax rax cax cay caz clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z w rite c o mmand bank a activate c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a the write data is m a sked w i th a z e r o clo c k laten c y t h e read data is m a sked with a two c l o c k laten c y
integrated silicon solution, inc. www.issi.com 43 rev. a 12/19/07 is42s32800 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 1 1 t 1 2 t 13 t 1 4 t 15 t 1 6 t 17 t 1 8 t 19 t 2 0 t 21 t2 2 t ck2 bw0 bw1 b x 0 b x 1 b y 1 ay0 bz0 rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 t rcd t ac2 cay rax rax cbw cbx c b y c a y cbz clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z activate c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a pre c harge c o m m and bank a activate c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b pre c harge c o m m and bank b figure 14.2.interleaving column read cycle (burst length=4,cas#latency=2)
44 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t1 0 t 1 1 t1 2 t 1 3 t1 4 t 1 5 t1 6 t 1 7 t1 8 t 1 9 t2 0 t 2 1 t2 2 t ck3 bx0 bx1 b y 0 b y 1 b z 1 a y0 ay 2 rax rax ax0 ax1 ax2 a x3 b z 0 a y 1 a y 3 t rcd t ac3 cax rbx rbx cbx cby cbz cay clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a rea d com m a n d bank a rea d c o mmand bank a pre c harge com m a n d bank a activate c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b pre c harge c o m m and bank b figure 14.3.interleaved column read cycle (burst length=4,cas#latency=3)
integrated silicon solution, inc. www.issi.com 45 rev. a 12/19/07 is42s32800 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck2 dbx0 dbx1 day0 rax rax dax0 dax1 dax2 dax3 day1 t rcd cax rb w rb w c b w cbx c b y cay t rrd t rp t wr t rp cbz dbz0 dbz1 dbz2 dbz3 dby0 dby1 dbw0 dbw1 clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z w rite c o mmand bank a w rite c o mmand bank a activate c o mmand bank a pre c harge c o mma n d bank a w rite c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b activate c o mmand bank b pre c harge com m a n d bank b figure 15.2.interleaved column write cycle (burst length=4,cas#latency=2)
46 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 15.3.interleaved column write cycle (burst length=4,cas#latency=3) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck3 d b w 0 d b w 1 dbx0 dbx1 d b y1 day0 rax rax dax0 dax1 dax2 dax3 d b y0 day1 t rcd cax r b w rb w cb w c b x c b y cay t rrd > t rrd(min) t rp t wr t wr(min) cbz dbz0 dbz1 dbz2 dbz3 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a w rite c o mmand bank a activate c o mmand bank a pre c harge c o m m and bank a w rite c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b activate c o mmand bank b pre c harge com m a n d bank b
integrated silicon solution, inc. www.issi.com 47 rev. a 12/19/07 is42s32800 figure 16.2.auto precharge after read burst (burst length=4,cas#latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 1 6 t 17 t 1 8 t 19 t 2 0 t 21 t 2 2 t ck2 bx0 bx1 bx2 bx3 a y 1 ay2 rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 rbx cbx rby ray cby by1 by2 by3 az0 az1 az2 cax rby raz caz raz clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z activate c o mmand bank a activate c o mmand bank a rea d c o mmand bank a activate c o mmand bank b activate c o mmand bank b hig h r e ad with auto precharge c o mmand bank b r e ad with auto precharge c o mmand bank b read with a u to precharge c o mmand bank a read with a u to precharge c o mmand bank a
48 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 16.3.auto precharge after read burst (burst length=4,cas#latency=3) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck3 bx0 bx1 bx2 bx3 a y 1 ay2 rax rax rbx ax0 ax1 ax2 ax3 a y 0 a y 3 by0 rbx cbx by1 by2 by3 cax rby cby rby ca y clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z activate c o mmand bank a rea d c o mmand bank a activate c o mmand bank b activate c o mmand bank b hig h read with a u to precharge c o mmand bank b r e ad with a u to precharge c o mmand bank b r e ad with auto precharge c o mmand bank a
integrated silicon solution, inc. www.issi.com 49 rev. a 12/19/07 is42s32800 figure 17.2.auto precharge after write burst (burst length=4,cas#latency=2) t 0t 1 t 2t 3t 4t 5t 6t 7 t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 dbx0 dbx1 dbx2 dbx3 day1 day2 rax rax rbx dax0 dax1 dax2 dax3 day0 day3 cbx cay rby cby rby daz0 daz1 daz2 daz3 cax rbx caz raz raz dby0 dby1 dby2 dby3 clk cke cs# ras# cas# we# bs0,1 a10 a 0-a9 dqm dq hi-z w rite c o mmand bank a activate c o mmand bank a activate c o mmand bank a activate c o mmand bank b activate c o mmand bank b hig h wr i t e with auto precharge c o mmand bank b w rite with auto precharge c o mmand bank b wr i t e with au to precharge c o mmand bank a wr i t e with auto precharge c o mmand bank a
50 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 17.3.auto precharge after write burst (burst length=4,cas#latency=3) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck3 dbx0 dbx1 dbx2 dbx3 day1 day2 rax rax rbx dax0 dax1 dax2 dax3 day0 day3 cbx cay cax rbx cby rby rby ? dby0 dby1 dby2 dby3 clk cke cs# ras # cas # we# bs0,1 a9 a 0 -a9 dqm dq hi-z wr i t e c o mmand bank a activate c o mmand bank a activate c o mmand bank b activate c o mmand bank b hig h w rite with a u to precharge c o mmand bank b w rite with auto precharge c o mmand bank b wr i t e with au to precharge c o mmand bank a
integrated silicon solution, inc. www.issi.com 51 rev. a 12/19/07 is42s32800 figure 18.2.full page read cycle (burst length=full page,cas#latency=2) t0 t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 13 t 1 4 t 15 t 1 6 t 17 t 1 8 t 19 t 2 0 t 21 t 2 2 a x ax + 1 bx bx + 1 bx + 3 bx + 4 rax rax ax + 1 a x + 2 ax-2 ax- 1 b x+ 2 b x+ 5 cbx rbx cax rby rby ax bx + 6 t ck2 t rp rbx clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a activate c o mmand bank b activate c o mmand bank b pre c harge c o mma n d bank b hig h burst stop c o mmand the burst counter wraps from the highest order page address back to zero during this time interval rea d c o mmand bank a rea d c o mmand bank b f u l l page burst ope r a tion does not t e r m i n a t e when the burst len g th i s s a t i s fied; the burst c o unte r incre m e n ts a nd continu e s burst i n g beginning w i th the s t a r ting a d d r ess .
52 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 18.3.full page read cycle (burst length=full page,cas#latency=3) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 bx bx+1 rax rax ax+1 ax-2 ax-1 cbx rbx cax rby rby ax t ck3 t rp rbx ax+2 a x ax+1 bx+2 bx+3 bx+4 bx+5 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z activate c o mmand bank a activate c o mmand bank b activate c o mmand bank b pre c harge com m a n d bank b hig h burst stop com m a n d the burst counter wraps from the highest order page address back to zero during this time interval rea d com m a n d bank a rea d c o mmand bank b f u l l page burst ope r a t ion does not t e rmina t e when t h e b u r s t l e n g t h is sati s f i e d ; the burst count e r increm e n ts a nd continues burst i ng b e g i n n i n g w i t h the st artin g address .
integrated silicon solution, inc. www.issi.com 53 rev. a 12/19/07 is42s32800 figure 19.2.full page write cycle (burst length=full page,cas#latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t1 0 t 1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 rax rax cbx rbx cax rby rby t ck2 5 rbx dax dax+1 dax+2 dax+3 dax-1 dax dax+1 dbx dbx+1 dbx+2 dbx+3 dbx+4 dbx+5 dbx+6 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z w rite c o mmand bank a activate c o mmand bank a w rite c o mmand bank b activate c o mmand bank b activate c o mmand bank b pre c harge com m a n d bank b hig h burst stop c o mmand data i s i g nore d full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. the burst counter wraps from the highest order page address back to zero during this time interval
54 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 19.3.full page write cycle (burst length=full page,cas#latency=3) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 rax rax cbx rbx cax rby rby t ck3 rbx da ta i s i g nor ed dax dax+1 dax+2 dax+3 dax-1 dax dax+1 dbx dbx+1 dbx+3 dbx+4 dbx+5 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hi-z hig h w rite c o mmand bank a activate c o mmand bank a w rite c o mmand bank b activate c o mmand bank b the b u r s t c o u n t e r w r a p s fro m t h e h i ghes t order page addres s b a c k to z e r o during thi s t i m e i n te r v a l activate c o mmand bank b pre c harge c o m m and bank b burst stop com m a n d f u l l page b u rst oper a t i on doe s not te r m i n a t e when the burst len g th i s s a tisf i ed; the burs t cou n t e r i n crem e n ts and contin u e s b u r sting begi n n i ng w i t h the s t a r t i ng addres s .
integrated silicon solution, inc. www.issi.com 55 rev. a 12/19/07 is42s32800 figure 20.byte write operation (burst length=4,cas#latency=2) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 rax rax cay cax t ck2 caz ax0 ax1 ax2 ax1 ax2 ax3 day1 day2 day0 day1 day3 az1 az2 az1 az2 az3 w rite c o mmand bank a clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 hig h activate c o mmand bank a c o mmand bank a d qm0 d qm1,2,3 dq0 - dq7 d q 8 - dq15 rea d c o mmand bank a rea d a r e m a sked u p p e r 3 bytes a r e m a sked u p p e r 3 bytes lower byte is maske d lower byte is maske d lower byte is maske d
56 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 22.full page random column read (burst length=full page,cas#latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 2 2 t ck2 a x 0 b x 0 ay0 ay1 by0 by1 az0 az1 az2 bz0 bz1 bz2 t rp t rrd t rcd rax rax rbx rbx cax cbx c a y c b y caz cbz rbw rbw clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq c o mmand bank b activate c o mmand bank a activate c o mmand bank b activate c o mmand bank b rea d c o mmand bank b rea d c o mmand bank b rea d c o mmand bank a rea d c o mmand bank a rea d c o mmand bank a rea d pre c harge c o m m a nd bank b (precha r g e t e m i n a tion )
integrated silicon solution, inc. www.issi.com 57 rev. a 12/19/07 is42s32800 figure 23.full page random column write (burst length=full page,cas#latency=2) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck2 dax0 dbx0 day0 day1 dby0 dby1 daz0 daz1 daz2 dbz 0 t rp t rrd t rcd rax rax rbx rbx cax c b x cay cby caz cbz rbw rbw t wr dbz 1 dbz 2 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq w rite c o mmand bank a w rite c o mmand bank a wr i t e c o mmand bank a activate c o mmand bank a w rite c o mmand bank b w rite c o mmand bank b w rite c o mmand bank b activate c o mmand bank b activate c o mmand bank b pre c harge c o m m a nd bank b (precha r g e t e m i n a tion ) w rite data is maske d
58 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 figure 24.2.precharge termination of a burst (burst length=8 or full page,cas#latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t1 4 t1 5 t1 6 t1 7 t1 8 t1 9 t2 0 t2 1 t2 2 t ck2 dax0 dax1 dax2 dax3 ay2 ay0 ay1 rax rax ray cax ray cay az0 az1 az2 t wr t rp t rp raz caz t rp raz clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hig h w rite c o mmand bank a activate c o mmand bank a activate c o mmand bank a activate c o mmand bank a c o mmand bank a pre c harge com m a n d bank a pre c harge com m a n d bank a pre c harge com m a n d bank a rea d c o mmand bank a rea d p r echar g e t e r m i n ati o n o f a write burst. p r e c h a r g e t e rmina t i o n of a read b u r s t . w rite d a t a i s m a s k e d .
integrated silicon solution, inc. www.issi.com 59 rev. a 12/19/07 is42s32800 figure 24.3.precharge termination of a burst (burst length=4,8 or full page,cas#latency=3) t 0t 1 t 2t 3t 4t 5t 6t 7t 8t 9t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t ck3 dax0 ay0 ay1 ay2 rax rax ray cax ray cay t wr t rp t rp raz raz dax1 clk cke cs# ras # cas # we# bs0,1 a10 a 0 -a9 dqm dq hig h w rite c o mmand bank a c o mmand bank a activate c o mmand bank a activate c o mmand bank a activate c o mmand bank a pre c harge com m a n d bank a pre c harge com m a n d bank a w rite data is maske d p r e c h a r g e t e r m i n a t i o n of a write burst p r e c h a r g e t e rmina t i o n of a r e a d burst rea d
60 integrated silicon solution, inc. www.issi.com rev. a 12/19/07 is42s32800 ordering information commercial range: 0c to +70c frequency speed (ns) order part no. package 166 mhz 6 is42s32800-6tl 400 mil tsop-ii, lead-free 166 mhz 6 is42s32800-6bl 8 x13mm bga, lead-free 143 mhz 7 is42s32800-7tl 400 mil tsop-ii, lead-free 143 mhz 7 is42s32800-7bl 8 x13mm bga, lead-free industrial range: -40c to +85c frequency speed (ns) order part no. package 166 mhz 6 is42s32800-6tli 400 mil tsop-ii, lead-free 166 mhz 6 is42s32800-6bli 8 x13mm bga, lead-free 143 mhz 7 is42s32800-7tli 400 mil tsop-ii, lead-free 143 mhz 7 IS42S32800-7BLI 8 x13mm bga, lead-free
packaging information integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/31/07 copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (90-ball) mbga - 8mm x 13mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 90 a ? ? 1.45 ? ? 0.057 a1 0.25 ? 0.40 0.01 ? 0.016 d 12.90 13.00 13.10 0.508 0.512 0.516 d1 ? 11.20 ? ? 0.441 ? e 7.90 8.00 8.10 0.311 0.315 0.319 e1 ? 6.40 ? ? 0.252 ? e ? 0.80 ? ? 0.031 ? 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r ? 0.45 + 0.10/?0.05 (90x) d e e a1 seating plane a d1 e1 e notes: 1. controlling dimensions are in millimeters. 2. 0.8 mm ball pitch
packaging information integrated silicon solution, inc. 1 rev. d 03/13/07 plastic tsop 54?pin, 86-pin package code: t (type ii) plastic tsop (t - type ii) millimeters inches symbol min max min max ref. std. no. leads (n) 54 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 ? ? ? ? b 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.0083 d 22.02 22.42 0.867 0.8827 e1 10.03 10.29 0.395 0.405 e 11.56 11.96 0.455 0.471 e 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 l1 ? ? ? ? zd 0.71 ref 0 8 0 8 d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches symbol min max min max ref. std. no. leads (n) 86 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.12 0.21 0.005 0.008 d 22.02 22.42 0.867 0.8827 e1 10.03 10.29 0.395 0.405 e 11.56 11.96 0.455 0.471 e 0.50 bsc 0.020 bsc l 0.40 0.60 0.016 0.024 l1 0.80 ref 0.031 ref zd 0.61 ref 0.024 bsc 0 8 0 8

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